1. Field of the Invention
The present invention relates to a method for forming an interconnection for receiving bumps or balls of a semiconductor device for testing or burn-in of the device. In particular, the present invention relates to a method for forming sloped wall, metal-lined interconnections to receive and contain portions of solder balls of a semiconductor device therein.
2. State of the Art
Integrated circuit devices are well-known in the prior art. Such devices, or so-called xe2x80x9csemiconductor dice,xe2x80x9d may include a large number of active semiconductor components (such as diodes, transistors) in combination with (e.g., in one or more circuits) various passive components (such as capacitors, resistors), all residing on a xe2x80x9csemiconductor chipxe2x80x9d or die of silicon or, less typically, gallium arsenide or indium phosphide. The combination of components results in a semiconductor or integrated circuit die which performs one or more specific functions, such as a microprocessor die or a memory die, the latter as exemplified by ROM, PROM, EPROM, EEPROM, DRAM and SRAM dice.
Such semiconductor dice are normally designed to be supported or carried in an encapsulant or other package and normally have a plurality of externally-accessible connection elements in the form of solder balls, pins or leads, to which the circuits on each semiconductor die are electrically connected within the package to access other electronic components employed in combination with each semiconductor die. Bond pads on the active surface of a die may be directly in contact with the connection elements, or connected thereto with intermediate elements such as bond wires or TAB (Tape Automated Bonding, or flex circuit) connections, or rerouting traces extending to remote locations on the die active surface. An encapsulant is usually a filled polymer compound transfer molded about the semiconductor die to provide mechanical support and environmental protection for the semiconductor die, may incorporate a heat sink in contact with the die, and is normally square or rectangular in shape.
Bare semiconductor dice are usually tested at least for continuity, and often more extensively, during the semiconductor die fabrication process and before packaging. Such more extensive testing may be, and has been, accomplished by placing a bare semiconductor die in a temporary package having terminals aligned with the terminals (bond pads) of the semiconductor die to provide electrical access to the circuits on the semiconductor die and subjecting the semiconductor die via the assembled temporary package to burn-in and discrete testing. Such temporary packages may also be used to test entire semiconductor wafers prior to singulating the semiconductor wafers into individual semiconductor dice. Exemplary state-of-the-art fixtures and temporary packages for semiconductor die testing are disclosed in U.S. Pat. Nos. 5,367,253; 5,519,332; 5,448,165; 5,475,317; 5,468,157; 5,468,158; 5,483,174; 5,451,165; 5,479,105; 5,088,190; and 5,073,117. U.S. Pat. Nos. 5,367,253 and 5,519,332, assigned to the assignee of the present application, are each hereby incorporated herein for all purposes by this reference.
Discrete testing includes testing the semiconductor dice for speed and for errors which may occur after fabrication and after burn-in. Burn-in is a reliability test of a semiconductor die to identify physical and electrical defects which would cause the semiconductor die to fail to perform to specifications or to fail altogether before its normal operational life cycle is reached. Thus, the semiconductor die is subjected to an initial heavy duty cycle which elicits latent silicon defects. Burn-in testing is usually conducted at elevated potentials and for a prolonged period of time, typically 24 hours, at varying and reduced and elevated temperatures such as xe2x88x9215xc2x0 C. to 125xc2x0 C. to accelerate failure mechanisms. Semiconductor dice which survive discrete testing and burn-in are termed xe2x80x9cknown good die,xe2x80x9d or xe2x80x9cKGDxe2x80x9d.
As noted above, such testing is generally performed on bare semiconductor dice. However, while desirable for saving the cost of encapsulating bad semiconductor dice, testing bare, unpackaged semiconductor dice requires a significant amount of handling of these rather fragile structures. The temporary package must not only be compatible with test and burn-in procedures, but must also physically secure and electrically access the semiconductor die without damaging the semiconductor die. Similarly, alignment and assembly of a semiconductor die within the temporary package and disassembly after testing must be effected without semiconductor die damage. The small size of the semiconductor die itself and minute pitch (spacing) of the bond pads of the semiconductor die, as well as the fragile nature of the thin bond pads and the thin protective layer covering devices and circuit elements on the active surface of the semiconductor die, make this somewhat complex task extremely delicate. Performing these operations at high speeds with requisite accuracy and repeatability has proven beyond the capabilities of most state of the art equipment. Thus, since the encapsulant of a finished semiconductor die provides mechanical support and protection for the semiconductor die, in some instances, it is preferable to test and burn-in semiconductor dice after encapsulation.
A common finished semiconductor die package design is a flip-chip design. A flip chip semiconductor design comprises a pattern or array of terminations (e.g., bond pads or rerouting trace ends) spaced about an active surface of the semiconductor die for face-down mounting of the semiconductor die to a carrier substrate (such as a printed circuit board, FR4 board, ceramic substrate, or the like). Each termination has a minute solder ball or other conductive connection element disposed thereon for making a connection to a trace end or terminal on the carrier substrate. This arrangement of connection elements is usually referred to as a Ball Grid Array or xe2x80x9cBGAxe2x80x9d. The flip chip is attached to the substrate trace ends or terminals, which are arranged in a mirror-image of the BGA, by aligning the BGA thereover and (if solder balls are used) refluxing the solder balls for simultaneous permanent attachment and electrical communication of the semiconductor die to the carrier substrate conductors.
Such flip chips may be tested and/or burned-in prior to their permanent connection to a carrier substrate by placing each flip chip in a temporary package, such as those discussed above. As shown in FIG. 31, each solder ball 304 attached to a bond pad 302 of a flip chip-configured die 300 is in physical contact with a conductive trace 306 on a contact wall 308 of the temporary package. The conductive traces 306 transmit electrical signals to the die 300 for testing or burn-in. With such a temporary package, each solder ball 304 contacts each conductive trace 306 at only one contact point 310. With only one contact point 310 per ball 304, all of the stresses caused by biasing the die 300 to the contact wall 308 of the temporary package are concentrated on the one contact point 310 on each solder ball 304. These stresses can result in the solder balls 304 fracturing, dislodging from the bond pad 302, or otherwise damaging the flip chip 300.
Furthermore, such a temporary package configuration is also insensitive to ensuring electrical connection to the temporary package of non-spherical/irregularly shaped solder balls, or different sized balls, in the BGA. FIG. 32 illustrates an undersized solder ball 312 in the arrangement similar to that shown in FIG. 31. Elements common between FIG. 31 and FIG. 32 retain the same designation. The undersized solder ball 312 does not make contact with the conductive trace 306. This can give a false failure indication for the die, when, in reality, it could be xe2x80x9cgoodxe2x80x9d when an adequate connection is achieved when the undersized ball 312 is refluxed for permanent attachment to a carrier substrate. At the least, the die in question is initially rejected and must be retested to verify the source of the apparent failure.
Therefore, it would be advantageous to develop improved methods and apparatus for use with flip chip-retaining temporary packages, wherein the temporary packages can compensate for irregular solder ball shape and size, and reduce the risk of damage to the semiconductor device under test.
The present invention relates to a method of forming interconnections for a temporary contact with a semiconductor die, wafer or partial wafer, wherein the interconnections are capable of receiving solder balls for testing and burn-in. The present invention can be used for both wafer level and chip level testing and burn-in, and other probe card technology employing silicon inserts, as well as silicon KGD inserts.
The interconnections are designed to be formed in a recess, preferably a sloped-wall (either smooth or xe2x80x9csteppedxe2x80x9d) via. Such an interconnection design compensates for undersized or misshapen solder balls on the die under test to prevent a possible false failure indication for the die under test and reduces and reorients the stress on each solder ball when physical contact is made to its mating interconnection.
The inventive interconnections are preferably formed by etching the via in a passivation layer which is applied over an active surface of a semiconductor substrate, such as a silicon wafer, a partial wafer the same size or larger than a semiconductor die, or the like. The via may be etched to expose a conductive trace under or within the passivation layer. Alternately, the conductive trace may be formed after the via is formed, wherein the conductive trace is formed on the exposed surface of the passivation layer and extends into the via. A metal layer, preferably of an oxidation-resistant metal such as gold, platinum, palladium, or tungsten, is formed in the via to contact the associated conductive trace and complete the formation of the interconnection.
The interconnection is preferably circular as viewed from above to receive the spherical solder ball, which protrudes partially within the interconnect when placed in contact therewith. Preferably, approximately 10% to 50% of the total height of the solder ball, and preferably about 30% of the total height, will reside within the interconnect. With a spherical solder ball in a smooth sloped wall via interconnection, each solder ball will make a circular, or at least arcuate, line of contact with the interconnect surface about a periphery of the solder ball, rather than a single contact point. The circular contact distributes the force on the solder ball when the semiconductor substrate is biased against the insert carrying the interconnection in the temporary package, making damage to the solder ball or underlying bond pad less likely. Further, any oxide layer formed on the exterior surface of the solder ball will be more easily penetrated by the line of contact than through a single contact point effected with prior art interconnections.
With a solder ball received in a stepped-wall interconnection according to the invention, the solder ball may make multiple circular or at least arcuate contacts with the edges of the steps of the stepped interconnection, again facilitating electrical communication and piercing any oxide layer on the solder ball. Such multiple arcuate contacts further distribute the force applied to the solder ball during package assembly and subsequent testing.
In one embodiment of the invention, multiple passivation and trace layers are employed to accommodate small-pitched connection element arrays having as many as a thousand or more inputs and outputs (xe2x80x9cI/Osxe2x80x9d).